The present invention relates to apparatuses and methods for manufacturing a semiconductor, and more particularly, to non-uniform ion implantation apparatuses and methods, which enable impurity ions to be implanted at different doses in different regions of a wafer.
Generally, when manufacturing semiconductor devices such as Dynamic Random Access Memories (DRAMs), many processes are required. The these processes include a deposition process, an etching process, an ion implantation process, etc., and are typically performed for each wafer. Among these processes, the ion implantation process is a process performed in a way of accelerating dopant ions such as boron, arsenic ions, and the like using a strong electric field to pass through the surface of the wafer, thereby changing electric properties of the material through the ion implantation.
FIG. 1 is a schematic view illustrating a conventional ion implantation apparatus for this process.
Referring to FIG. 1, the conventional ion implantation apparatus includes a quadrupole magnet assembly 110, an X-scanner 120, a beam balancer 130, and an accelerator 140. More specifically, the quadrupole magnet assembly 110 serves to expand and reduce an ion beam 102 delivered from an ion beam source (not shown), and includes quadrupole magnets to generate a magnetic field in a gap between four magnetic poles. The quadrupole magnet assembly 110 includes first and second magnet assemblies 111 and 112, each having two S-poles and two N-poles. The X-scanner 120 scans the ion beam 102 in an X direction in order to uniformly distribute the ion beam 102 on a wafer 101. The beam balancer 130 serves to equate a parallel optical path in reference to ion beam 102. The accelerator 140 serves to accelerate charged particles, and can be positioned in front of the X-scanner 120 in some cases without being limited to a particular position, as shown in FIG. 1. With the conventional ion implantation apparatus described above, the ion beam 102 is scanned over the surface of the wafer 101 in the X direction, and at this time, the wafer 101 is moved in a Y direction in order to ensure ion implantation on the entire surface of the wafer 101.
FIG. 2 is a view illustrating a device for scanning the wafer 101 in the Y direction.
Referring to FIG. 2, a table (not shown) to support the wafer 101 is connected to a Y-driving shaft 210, which is connected to a driving unit 220. Operation of the driving unit 220 causes the Y-driving shaft 210 to move in the Y direction, as shown in arrow 211 of FIG. 2. While the wafer 101 moves in the Y direction, the ion beam 102 is scanned over the wafer 101 in the X direction. During this process, first and second wide ion beam detectors 231 and 232 respectively positioned in front and rear of the wafer 101 detect a dose of the implanted impurity ions, and supply information for controlling the dose of the impurity ions.
However, if the ion implantation is performed using the conventional ion implantation apparatus as described above, the impurity ions are implanted with near uniform concentration over the entirety of the wafer 101. In terms of the ion implantation only, this result is desirable, but when considered in relation to other unit processes, this result can be undesirable. In other words, after performing various unit processes, it can be easily found that these unit processes should not be uniformly performed over the entirety of the wafer, causing undesirable results, such as an undesired thickness of layers deposited on the wafer, an undesired etching rate, and the like. This is attributed to the fact that various parameters of each unit process cannot be accurately controlled. Thus, it is the actual circumstance in the art that fabrication errors may be provided due to unexpected or inaccurately controlled parameters during the process.
For example, when forming a gate electrode, a critical dimension (“CD”) indicating the width of the gate electrode can be varied depending on positions on the wafer. For example, the gate electrode can have a higher CD at a central region of the wafer, and a lower CD at the periphery of the wafer, or vice versa. As described above, the variation in thickness as described above is caused by inaccurate control of the various parameters of the unit processes. As such, if the CD of the gate electrode is higher at the central region of the wafer than at the periphery of the wafer, the threshold voltage of the device is also higher at the central region of the wafer than at the periphery of the wafer. If the CD of the gate electrode is lower at the central region of the wafer than at the periphery of the wafer, the threshold voltage of the device is lower at the central region of the wafer than at the periphery of the wafer.
A difference in CD of the gate electrode depending on the position on the wafer results in certain issues as an integration degree of devices on the wafer is increased. For example, when a minimally acceptable CD of the gate electrode is 200 nm, a reduction in yield is not significant even if ±10% distribution of CD is determined to be defective. However, when the minimally acceptable CD of the gate electrode is 100 nm, the reduction in yield becomes significant if ±10% distribution of CD is determined to be defective. Thus, when the minimally acceptable CD of the gate electrode is 100 nm, the distribution of CD as a reference for determination of defective items should be determined within a narrower range, for example, ±5%, and even in this case, the reduction in yield may still be significant due to the decrease in fabrication margin.
Thus, instead of accepting the difference in CD of the gate electrode on the wafer due to restriction of the unit processes, a non-uniform ion implantation method has recently been suggested wherein non-uniform implantation of impurity ions for compensation of the difference provides uniform characteristics over the entirety of the wafer. As described above, when the CD of the gate electrode is higher at the central region of the wafer than at the periphery of the wafer, the threshold voltage of the device is also higher at the central region of the wafer than at the periphery of the wafer. In this case, with the non-uniform ion implantation method, the impurity ions are implanted to a higher concentration at the central region of the wafer, and are implanted to a lower concentration at the periphery of the wafer in order to provide uniform characteristics over the entire surface of the wafer. On the contrary, when the CD of the gate electrode is lower at the central region of the wafer than at the periphery of the wafer, the threshold voltage of the device is lower at the central region of the wafer than at the periphery of the wafer. In this case, with the non-uniform ion implantation method, the impurity ions are implanted to a lower concentration at the central region of the wafer, and are implanted to a higher concentration at the periphery of the wafer in order to provide uniform characteristics over the entirety of the wafer. However, most of the conventional non-uniform ion implantation methods have difficulties in that a border between the region to be doped to a higher concentration and a region to be doped to a lower concentration is unclearly formed, and thus, they cannot be easily applied to actual processes.